In the processing of a substrate to fabricate circuits and displays, the substrate is typically exposed to an energized process gas capable of depositing or etching material on the substrate. In chemical vapor deposition (CVD) processes, process gas energized by a high frequency voltage or microwave energy is used to deposit material on the substrate, which may be a layer, a filling of contact holes, or other selective deposition structures. The deposited layer can be etched or otherwise processed to form active and passive devices on the substrate, such as for example, metal-oxide-semiconductor field effect transistors (MOSFETs) and other devices. A MOSFET typically has a source region, a drain region, and a channel region between the source and drain. In the MOSFET device, a gate electrode is formed above and separated from the channel by a gate dielectric to control conduction between the source and drain.
The performance of such devices can be improved by, for example, reducing supply voltage, gate dielectric thickness, or channel length. However, such conventional methods face mounting problems as the size and spacing of the devices become ever smaller. For example, at very small channel lengths, the advantages of reducing channel length to increase the number of transistors per unit area and saturation current are offset by undesirable carrier velocity saturation effects. Similar benefits which are obtained from reducing gate dielectric thickness, such as decreased gate delay, are limited in small devices by increased gate leakage current and charge tunneling through the dielectric which can damage the transistor over time. Reducing supply voltage allows lower operating power levels but such reductions are also limited by the threshold voltage of the transistor.
In a relatively newly developed method of enhancing transistor performance, the atomic lattice of a deposited material is stressed to improve the electrical properties of the material itself, or of underlying or overlying material that is strained by the force applied by a stressed deposited material. Lattice strain can increase the carrier mobility of semiconductors, such as silicon, thereby increasing the saturation current of the doped silicon transistors to thereby improve their performance. For example, localized lattice strain can be induced in the channel region of the transistor by the deposition of component materials of the transistor which have internal compressive or tensile stresses. For example, silicon nitride materials used as etch stop materials and spacers for the silicide materials of a gate electrode can be deposited as stressed materials which induce a strain in the channel region of a transistor. The type of stress desirable in the deposited material depends upon the nature of the material being stressed. For example, in CMOS device fabrication, negative-channel (NMOS) doped regions are covered with a tensile stressed material having positive tensile stress; whereas positive channel MOS (PMOS) doped regions are covered with a compressive stressed material having negative stress values.
Thus, it is desirable to form stressed materials that have predetermined types of stresses, such as tensile or compressive stresses. It is further desirable to control the level of stress generated in the deposited material. It is also desirable to deposit such stressed materials to generate uniform localized stresses or strains in the substrate. It is also desirable to have a process that can form stressed materials over active or passive devices on the substrate without damaging the devices. It is still further desirable that the deposited films be highly conformal to underlying topography.
More ever, as device geometries of integrated circuits and transistors have decreased, the gate drive current required by the transistors has increased. A gate drive current of a transistor increases as its gate capacitance increases, and the gate capacitance of a transistor is equal to k*A/d, where k is the dielectric constant of the gate dielectric (which is usually silicon oxide), d is the dielectric thickness, and A is the gate contact area. Thus, decreasing the dielectric thickness and increasing the dielectric constant of the gate dielectric are two ways of increasing the gate capacitance and the drive current.
Attempts have been made to reduce the thickness of dielectrics, such as reducing the thickness of silicon dioxide (SiO2) dielectrics to below 20 Å. However, the use of SiO2 dielectrics with thicknesses below 20 Å often results in undesirable performance and decreased durability. Nitridation of the SiO2 layer has been employed as a way to reduce the thickness of the SiO2 dielectric layer to below 20 Å.
Forming dielectric layers on a substrate by chemical reaction of gases is one of the primary steps in the fabrication of modern semiconductor devices. These deposition processes are referred to as chemical vapor deposition (CVD). Plasma enhanced chemical vapor deposition (PECVD) uses plasma in combination with traditional CVD techniques.
CVD and PECVD processes help form vertical and horizontal interconnects. Damascene or dual damascene methods involve the deposition and patterning of one or more material layers. In the damascene method, the low k dielectric (i.e., having a dielectric constant (k) of less than 4.0) or other dielectric materials are deposited and pattern etched to form vertical interconnects, also known as vias, and horizontal interconnects, also known as lines.
However, when low k materials are used in damascene formation, it is difficult to produce features with little or no surface defects or feature deformation. During deposition, the material may overloaf, that is, deposit excess material on the shoulders of a via and deposit too little material in the base of the via, forming a shape that looks like the side of a loaf of bread. The phenomena is also known as footing because the base of the via has a profile that looks like a foot. In extreme cases, the shoulders of a via may merge to form a joined, sealed surface across the top of the via. The film thickness non-uniformity across the wafer can negatively impact the drive current improvement from one device to another. Modulating the process parameters alone does not significantly improve the step coverage and pattern loading problems.
Therefore, a need exists in the art for a deposition method useful for semiconductor processing, which provides a conformal film over formed features.